Heterogeneous Reconfigurable Architecture Design: An Optimisation Approach

This thesis examines methods for generation of heterogeneous reconfigurable hardware based on formal optimisation methods. As reconfigurable hardware has evolved, an increasing number of different embedded component types have been made available on reconfigurable devices. Existing techniques for generating hardware and analysing the advantages of different embedded components are heuristic based, and hence not provably optimal, indeed, even the meaning of “optimal” in such a setting is disputed. Using formal optimisation in the form of integer linear programming, it is possible to determine the advantages of such components analytically for the first time. Moreover, it is possible to use such techniques to determine technology mapping and floorplanning of target designs and floorplanning of architectures concurrently and optimally. In addition, this thesis covers aspects concerning the scalability of integer linear programming. Heuristic methods to solve larger, more complex problems are detailed. The heuristics have been developed so as to be scalable for large, complex designs. The methods introduced in this thesis allow re-